WEBVTT
Kind: captions
Language: en
00:00:24.689 --> 00:00:32.550
Welcome to our 9th lecture of facts devices
today we shall continue with the PWM techniques
00:00:32.550 --> 00:00:39.690
for the multilevel inverter. So, we were
discussing on previous class with the level
00:00:39.690 --> 00:00:46.460
shifted PWM. So, what is level shifted PWM,
the device the basic features of the level
00:00:46.460 --> 00:00:52.620
shifted PWM is said that the device switching
frequency is obtained by multiplying the number
00:00:52.620 --> 00:00:58.190
of getting pulses per cycle by the frequency
of the modulating wave .
00:00:58.190 --> 00:01:06.890
Moreover the device switching frequency is
not same for devices in a different bridge
00:01:06.890 --> 00:01:14.420
configuration. So, this is one of the disadvantage
of it the duty cycle of the actually RMS current
00:01:14.420 --> 00:01:19.850
rating and the all those things will be different
for the different switches of the H-bridge
00:01:19.850 --> 00:01:24.070
.
And, output voltage of the H bridge this H
00:01:24.070 --> 00:01:32.190
1 2 and H 3 all are different and in level
shifted PWM the device switching frequency
00:01:32.190 --> 00:01:38.530
is not equal for the carrier frequency. So,
this is advantages or disadvantageous. So,
00:01:38.530 --> 00:01:43.910
if it is lower frequency we can lower
frequency and the higher current rating we
00:01:43.910 --> 00:01:49.819
can choose a particular devices and we can
choose a if there is a lower power rating
00:01:49.819 --> 00:01:54.890
and high frequency, we can choose a different
current it is there is a advantage, we can
00:01:54.890 --> 00:01:58.979
we uses the advantages we also even though
it seems to be a disadvantageous.
00:01:58.979 --> 00:02:02.800
The inverter switching frequency equal to
the carrier wave frequency there is no change
00:02:02.800 --> 00:02:12.170
in that and average device switching frequency
will be given by actually f cr by m minus
00:02:12.170 --> 00:02:18.810
1 where m is the level of the inverter. Now,
let us see that what happened? In case of
00:02:18.810 --> 00:02:29.280
the sidebands, and we can see that this is
basically the neutral point or the phase
00:02:29.280 --> 00:02:36.790
voltage and this is basically the line voltage.
And, it is basically approximated by the it
00:02:36.790 --> 00:02:43.250
is the ratio of V A N by V d.
So, the dominated harmonics it can be seen
00:02:43.250 --> 00:02:53.460
that V A A N, that is the neutral voltage
and appear as sideband centred around m f.
00:02:53.460 --> 00:03:04.260
So, you will get the THD an around of basically
16 18.6 percent quite high PWM quite high
00:03:04.260 --> 00:03:15.319
THD . And in this case you will find that
it is harbour around here here here. We have
00:03:15.319 --> 00:03:21.130
chosen the value of the m f in this case as
60. For example, if you are operating in a
00:03:21.130 --> 00:03:28.690
50 kilohertz normal power supply frequency
60 time this is the 3 kilohertz is your switching
00:03:28.690 --> 00:03:34.260
frequency .
So, what happen here the inverter phase voltage
00:03:34.260 --> 00:03:40.440
considered as triplen harmonic? Though it
will be not be reflected to your line harmonics
00:03:40.440 --> 00:03:49.700
. And such m f and such as m f this
is for this reason m f plus minus 6 with the
00:03:49.700 --> 00:03:56.880
being a dominating harmonic or the triplen
harmonics are are absent in the line voltage
00:03:56.880 --> 00:04:04.090
A B n it is quite clear .
Now, what are the actually take away from
00:04:04.090 --> 00:04:11.800
this actually level shifted PWM, conduction
time of this devices are not continuous and
00:04:11.800 --> 00:04:18.549
it is distributed among switches. So, thermal
rating of the devices can be improved. So,
00:04:18.549 --> 00:04:25.430
we can use optimally their thermal rating.
Switches and so, for this reason the second
00:04:25.430 --> 00:04:31.319
conclusion comes switch devices and the average
for handle by the each switch module are not
00:04:31.319 --> 00:04:38.500
evenly distributed. This is one of the disadvantage
of it and we required to manage as much as
00:04:38.500 --> 00:04:46.671
possible by the control logic.
And, it causes current distortion and the
00:04:46.671 --> 00:04:54.220
input site that is not also advantageous.
Because you know that the mf plus minus 6
00:04:54.220 --> 00:05:00.770
is present into the harmonic. And to evenly
distributing switching and the conduction
00:05:00.770 --> 00:05:07.720
loss the switching pattern should be rotated
among the H-bridge cell, that is the that
00:05:07.720 --> 00:05:12.960
that is something you required to manipulate
with the with control strategy.
00:05:12.960 --> 00:05:18.670
So, first of all you try to spend more amount
of current through a particular H-bridge and
00:05:18.670 --> 00:05:25.350
maybe you know after 2 cycle later the sequence
may change. And accordingly actually you will
00:05:25.350 --> 00:05:31.889
find that you will distribute the switching
losses or the device rating among all the
00:05:31.889 --> 00:05:46.160
H-bridge connected in series. So, this is
the sideband PWM with even power distribution.
00:05:46.160 --> 00:05:55.960
See, that please try to understand it the
problem of you know uneven power distributions,
00:05:55.960 --> 00:06:06.460
in this line shifted PWM is solved by alternating
phase shift carrier of the each module.
00:06:06.460 --> 00:06:13.270
And, the rotational levels are perform separately
for positive as well as a negative carrier.
00:06:13.270 --> 00:06:19.960
See, that here you know this is the carrier
wave. So, you can see that this is this is
00:06:19.960 --> 00:06:27.520
the zone where it hardly actually crosses,
ultimately switching is mostly done on this
00:06:27.520 --> 00:06:34.580
part of it and in this part also this is over
modulation for this wave. So, there is no
00:06:34.580 --> 00:06:39.389
actually no switching if it is it is a discontinuously
on for this duration .
00:06:39.389 --> 00:06:51.640
Similarly, in this duration it is continuously
off. Same happen to the lower cycle. So, these
00:06:51.640 --> 00:06:58.160
can be you know something some way or other
can be controlled. So, look this is the actually
00:06:58.160 --> 00:07:04.949
the point it is crosses, thereafter it will
point it will crosses, something like. So,
00:07:04.949 --> 00:07:11.040
this is the carrier this is the control signals
for switch 1, this is for switch 2, this is
00:07:11.040 --> 00:07:19.320
for switch 3, and this is for switch 4 you
can see that this carriers are basically crossing.
00:07:19.320 --> 00:07:28.320
But, if you interchange in some half cycle
you give c r 1 and c r 2 and we can actually
00:07:28.320 --> 00:07:35.900
optimise the losses. See that what happen
here? This is the basically the v reference
00:07:35.900 --> 00:07:43.030
that required to be tracked the modulating
wave and you know you will compare with the
00:07:43.030 --> 00:07:49.970
c r 1 and ultimately you will have the c r
prime, and accordingly when when this value
00:07:49.970 --> 00:07:58.370
is v star or the v reference is more than
this vcr delta. So, switch S 1 will be
00:07:58.370 --> 00:08:04.600
on.
Similarly, see S 2 when we on when this reference
00:08:04.600 --> 00:08:12.210
voltage is greater than the v c r 2. So, then
subsequently other switches will be on. So,
00:08:12.210 --> 00:08:19.960
what we can how you will generate it a square
wave signal for the half of the carrier frequency,
00:08:19.960 --> 00:08:26.789
with with appropriate amplitude to provide
the offset added to the each carrier wave.
00:08:26.789 --> 00:08:33.159
So, you will add up. So, it will be shifting
positive and the negative half cycle accordingly
00:08:33.159 --> 00:08:41.380
. As the number of voltage level increases
the square of signal has to be replaced by
00:08:41.380 --> 00:08:47.339
the steer case waveform. Depending on the
multilevel inverter if it is more than
00:08:47.339 --> 00:08:52.709
3 level you required to be a steer case. And
the output of the waveform will be same as
00:08:52.709 --> 00:09:01.839
that of the LSPWM only H-bridge output output
voltage will change, in that way this is the
00:09:01.839 --> 00:09:11.800
simple way to implement LSPWM .
Now, let us combine L S and P S then what
00:09:11.800 --> 00:09:20.990
will happen then it is said to be the hybrid
PWM. Where you will find that basically there
00:09:20.990 --> 00:09:26.840
is a there will be a minor image form here,
actually there is a phase opposition disposition.
00:09:26.840 --> 00:09:33.320
So, this and these are in a same phase, but
they are phase shifted, but they are sorry
00:09:33.320 --> 00:09:38.720
they are in a same phase, but the shifted
by the magnitude.
00:09:38.720 --> 00:09:49.480
So, hybrid phase shifted and the level shifted
PWM I mean when you combine the phase
00:09:49.480 --> 00:09:57.380
shift and the level shift you get the hybrid
1, carriers are subjected to vertical as well
00:09:57.380 --> 00:10:05.440
as the horizontal shift . So, see that this
black line bolded and this black line dotted
00:10:05.440 --> 00:10:15.980
are the vertically shifted . And of course,
you can see that if they are they are also
00:10:15.980 --> 00:10:23.390
can be shifted there can then it is a phase
opposition only 2 bands are from the modulation.
00:10:23.390 --> 00:10:33.140
So, you automatically this actually the form
so, this so, what happened in this case
00:10:33.140 --> 00:10:39.269
the average device of the device switching
frequency of the modulating hybrid modulation
00:10:39.269 --> 00:10:47.080
is half of the phase shifted PWM. And the
dominating harmonic thus you know will be
00:10:47.080 --> 00:10:59.220
centred around m minus 1 by 2 into m f, where
m f is the actually the modulating frequency
00:10:59.220 --> 00:11:04.040
index.
The hybrid modulating frequency index with
00:11:04.040 --> 00:11:10.080
cascade multilevel inverter will have the
following features this technique involves,
00:11:10.080 --> 00:11:15.700
both high frequency and the low frequency
switching, high power modules are operated
00:11:15.700 --> 00:11:23.380
at a low frequency, to reduce the switching
loss we can choose a higher power device
00:11:23.380 --> 00:11:28.590
with reduced switching loss, where it is switching
frequency will be less because you know that
00:11:28.590 --> 00:11:32.310
most of the cases are IGBT IGDBT I mean current
real.
00:11:32.310 --> 00:11:38.820
So, if the rating of the IGBT is more then
it is switching frequency is been reduced
00:11:38.820 --> 00:11:48.360
. Where low power module is controlled by
the unipolar PWM. So, this is a very simplest
00:11:48.360 --> 00:11:53.580
way to implement it what you have studied
in the 2 level inverter this method is only
00:11:53.580 --> 00:12:02.710
visible if DC link voltage of the of the higher
power modules all the integer multiple of
00:12:02.710 --> 00:12:06.420
the small one.
So, we have to. So, if you put 40 another
00:12:06.420 --> 00:12:11.630
you required to put 80 and so on something
like that and this kind of application is
00:12:11.630 --> 00:12:19.050
highly visible in case of the solar inverter.
Solar inverter you can actually have a parallel,
00:12:19.050 --> 00:12:24.950
you can have a separate strings and string
size of the module can be changed by this
00:12:24.950 --> 00:12:34.110
equations and thus these are actually a perfect
fit for with this control strategy.
00:12:34.110 --> 00:12:43.230
Moreover, this 3 module inverter having this
is the reason you know V 3 should be less
00:12:43.230 --> 00:12:52.000
than to V 1 V 2 and again V 2 should be less
than equal to 2 V 1 in that way actually we
00:12:52.000 --> 00:12:58.490
required to make this consider this constraint
to be satisfied. So, V 3 should be greater
00:12:58.490 --> 00:13:08.340
than V 2 it should be greater than V 1. So,
how you will do that as I told you you know
00:13:08.340 --> 00:13:14.010
instead of square wave you will have a actually
steps kind of waveform. So, you will have
00:13:14.010 --> 00:13:24.850
a V 3. So, from there you have a control logic
it is something hysteresis loop in X axis.
00:13:24.850 --> 00:13:32.540
So, you will then thus you will have a v a
3 .
00:13:32.540 --> 00:13:43.600
And v a 3 actually will be subtracted from
V 3 and thus you get a v a 2 . And v a 2 again
00:13:43.600 --> 00:13:51.950
we will have a hysteresis loop in a control
cell same way it will generate v a 2 and again
00:13:51.950 --> 00:14:01.240
you will have this control cell and ultimately
you will get this this v a 1. And v a n
00:14:01.240 --> 00:14:11.149
will be summation of all the 3 voltages v
a 3 v a 2 and v a 1. If, there are 3 power
00:14:11.149 --> 00:14:18.589
module so, this is the logic. So, plus minus
H 3 should be equal to v a 1 plus v a 2 and
00:14:18.589 --> 00:14:23.780
H 2 should be equal to plus minus v a 1 something
like that.
00:14:23.780 --> 00:14:34.230
Now, see that hybrid PWM modulation. As we
have discussed the power output voltage van
00:14:34.230 --> 00:14:43.290
should be V a 1 V a 2 and V a 3. So, see that
you know this one is actually this should
00:14:43.290 --> 00:14:54.450
be the ultimate modulation wave wave form
and this one is your v a 3. And, you required
00:14:54.450 --> 00:15:04.160
to generate also V a 2 and this this blue
one is v a 2 and and and this one is v a 2.
00:15:04.160 --> 00:15:12.399
So, this difference of the step kind of waveform
is basically V 2 minus v a 3.
00:15:12.399 --> 00:15:19.051
Similarly, and you will find that there is
a less ripple. Here power handling this device
00:15:19.051 --> 00:15:26.050
will hold a maximum power handling and this
is the middleman in the road and you can see
00:15:26.050 --> 00:15:31.600
that there is a ripple. So, it has to handle
also the middle of the switching frequency.
00:15:31.600 --> 00:15:38.870
Same way v a 1 you will find that it is when
and thus it has to track this actually the
00:15:38.870 --> 00:15:44.779
error voltages and which will be high frequency.
For this reason it is a low power device with
00:15:44.779 --> 00:15:51.399
the high frequency it will be exactly fitting
this application. So, thus ultimately you
00:15:51.399 --> 00:15:59.760
will get actually this kind of waveform
in voltage and which can be eliminated with
00:15:59.760 --> 00:16:07.620
the help of actually low pass filter .
Now, we have discussed different kind of PWM
00:16:07.620 --> 00:16:15.019
technique, now let us discuss the same PWM
same space vector modulation technique, which
00:16:15.019 --> 00:16:23.440
we have discussed in case of PWM. In case
of the 2 level I was just extended to the
00:16:23.440 --> 00:16:32.019
3 level. We considered actually plus and minus
there or 0 and 1 there and here since actually
00:16:32.019 --> 00:16:40.000
we have 2 upper leg short then switches or
we will say that this state as P.
00:16:40.000 --> 00:16:49.160
And, when it is actually we have realise please
recall this actually this 3 level inverter
00:16:49.160 --> 00:16:54.540
with a triple throw single pole switch. So,
in this switch is connected at this position
00:16:54.540 --> 00:16:59.690
and this is the midpoint of the capacitor
and this is the point when it is connected
00:16:59.690 --> 00:17:10.039
this position . Then what happen then actually
it is connected to the P, when this switch
00:17:10.039 --> 00:17:16.919
is connected this position we say that it
is connected to 0 or opposition. And, similarly
00:17:16.919 --> 00:17:21.990
when it is connected to the lower of the dc
link voltage we will say that it is connected
00:17:21.990 --> 00:17:29.440
to the n.
Now, since it has to so, this had a 2 combination
00:17:29.440 --> 00:17:35.519
since there is a 2 switching combinations
for a leg 1 and 0. So, there is a possibility
00:17:35.519 --> 00:17:50.350
of the 8 state 0 0 0 to 1 1 0 0 to 1 1. Now,
in this case you will have actually 27 states.
00:17:50.350 --> 00:18:02.899
Now among this state we shall see that few
will generate the null vector and and total
00:18:02.899 --> 00:18:11.559
18 state will be there. And so, in that in
case of the 2 level inverter for the SPWM
00:18:11.559 --> 00:18:18.029
you know that actually 0 0 0 and 1 1 1 will
give you the null vector.
00:18:18.029 --> 00:18:22.759
But, here you will find many combination of
it to generate null vectors. So, you have
00:18:22.759 --> 00:18:31.859
a more redundancy with the switches and then
that is gives you more flexibility and the
00:18:31.859 --> 00:18:39.629
reliability . And, what you required to do
we required to find out the relation between
00:18:39.629 --> 00:18:45.200
the switching state and their corresponding
space vectors, the same procedure we have
00:18:45.200 --> 00:18:56.950
used for the 2 level inverter.
So, let us whatever we have discussed in the
00:18:56.950 --> 00:19:02.509
2 level same thing is applicable here based
on their magnitude of the voltage vector can
00:19:02.509 --> 00:19:11.419
be divided into the 4 groups. One is 0 vector
or null vector. So, these are basically when
00:19:11.419 --> 00:19:20.249
you 0 voltage is applied. So, this is actually
all the upper switches is closed or all the
00:19:20.249 --> 00:19:25.710
middle switches are closed that is 0 0 0 and
all the lower switches are closed .
00:19:25.710 --> 00:19:38.629
Similarly, there will be small vector these
are V 1 to V 6 having magnitude since you
00:19:38.629 --> 00:19:43.820
know that when when you we have talked about
the DC bus, we have talked about this is actually
00:19:43.820 --> 00:19:53.600
total voltage total voltage is 2 by 3 V dc.
So, in this case is small vector or half vector
00:19:53.600 --> 00:20:02.630
will call it then this value will be actually
V dc by 3. And each have a small vector with
00:20:02.630 --> 00:20:09.799
2 switching state 1 containing plus P.
And another containing minus e and therefore,
00:20:09.799 --> 00:20:18.419
ssscan be further furnish into P or N type
small vectors . Now, similarly we have a medium
00:20:18.419 --> 00:20:27.710
vector these are called half angle vector
sometimes. And, we denote them for 1 2
00:20:27.710 --> 00:20:40.919
from 7 to 12 and whose magnitude will be actually
V dc by 3 and it will be 30 degree. And there
00:20:40.919 --> 00:20:47.840
will be large vectors and which was the present
in case of the two-level inverter also and
00:20:47.840 --> 00:20:56.720
this will be present and that value will be
V dc by 3. If you only use this large vector
00:20:56.720 --> 00:21:01.499
then actually then this 3 level inverter falls
down to the two-level inverter.
00:21:01.499 --> 00:21:08.029
So, let us see that we have calculated the
time in case of the 3 level 2 level inverter
00:21:08.029 --> 00:21:19.929
can it be extended here. So, this is the diode
clamped 3 level inverter and this is the reference.
00:21:19.929 --> 00:21:28.090
So, see that PPP that is positive positive
positive then what is P, when S 1 and S 2
00:21:28.090 --> 00:21:45.749
is closed for a leg. So, NNN, that is all
the lower leg are closed and 0 0 0. In 3 combinations
00:21:45.749 --> 00:21:56.009
you will find that you are not applying any
voltage to the line. So, it is null vector
00:21:56.009 --> 00:22:10.919
. So, this is set to be the V 1, you can generate
V 1 with plus 0 0, that mean plus this and
00:22:10.919 --> 00:22:25.499
this or you can also use 0 N N, if you use
plus 0 0 we say that it is a P class of half
00:22:25.499 --> 00:22:30.640
vector and if you generate by ONN we say that
N class of half vector.
00:22:30.640 --> 00:22:39.529
Same way there will be a mirror image it is
OPP you can have or you have N 0 0, V 1 and
00:22:39.529 --> 00:22:49.320
V 4. So, see that this this vectors this
half vectors can be generated there is a 6
00:22:49.320 --> 00:22:54.840
half vectors and we have a 4 combinations.
So, you have a more amount of the flexibility
00:22:54.840 --> 00:23:08.490
. And uh you know considering that the phase
V a V c and a and till this 180 degree.
00:23:08.490 --> 00:23:22.340
Actually you can see here from this point
the phase a get positive till this time actually
00:23:22.340 --> 00:23:30.200
it lies positive. So, this is the basically
the this is basically the phase difference
00:23:30.200 --> 00:23:40.809
for positive phase or phase A. So, minus
60 degree to plus 60 degree .
00:23:40.809 --> 00:23:49.349
Similarly, you can see that for phase B
this P starts here and ends here and here
00:23:49.349 --> 00:23:59.039
actually for phase C phase C starts here as
well as ends here . So, we can we can actually
00:23:59.039 --> 00:24:04.509
find it out where is the actually the we can
find it out the voltage V and theta let us
00:24:04.509 --> 00:24:14.719
say you are here and I have shown it is here.
So, what happened here? You can think of that
00:24:14.719 --> 00:24:33.139
this voltage is made of V 1 V 7 and also V
13. And, what we required to do you know actually
00:24:33.139 --> 00:24:44.299
since since we can we we can think of
that this voltage this it is required to you
00:24:44.299 --> 00:24:51.969
and later shift is origin here and ultimately
when you shift is origin here. So, and you
00:24:51.969 --> 00:25:02.499
take this X X A X 7 and you will find that
this one this this can be treated as a
00:25:02.499 --> 00:25:09.460
2 level inverter. And same calculations what
you have done for the 3 level inverter is
00:25:09.460 --> 00:25:21.479
valid same way for for this leg also.
So, thus let us take out that portion of the
00:25:21.479 --> 00:25:28.389
triangle and find it out what should be the
value of a T 1 T 2 or in this case actually
00:25:28.389 --> 00:25:35.700
T a T b T s. So, dual time calculations for
the neutral point clamp converter is based
00:25:35.700 --> 00:25:39.609
on the volt second balance what we have done
in case same thing we have done in in case
00:25:39.609 --> 00:25:47.049
of the two-level inverter . The reference
vector V ref can be synthesised by the nearest
00:25:47.049 --> 00:25:53.450
3 stationary vectors, in this case we can
see that it is with V 1 it is applied for
00:25:53.450 --> 00:26:02.979
this time T a with V 2, it has been applied
for the time T b and V c, that is equal to
00:26:02.979 --> 00:26:07.570
T s and in between we have a null vector that
that will be there.
00:26:07.570 --> 00:26:16.999
So, we required to calculate same way the
T a T b T c and thus we required to know that
00:26:16.999 --> 00:26:27.070
for which time duration what will be applied
. And and you see that in between how it will
00:26:27.070 --> 00:26:43.789
work? So, when you apply when you apply PPP.
So, you your load configuration is this . Similarly,
00:26:43.789 --> 00:26:51.039
when you apply P 0 0 your load configuration
is this f s is connected to the positive of
00:26:51.039 --> 00:26:59.369
the DC bus voltage and it is connected to
0. Then you can also connect and that will
00:26:59.369 --> 00:27:08.440
also give you 0 that is 0NN so, you get this
voltage.
00:27:08.440 --> 00:27:15.539
Similarly, it is PON, then you get this kind
of configuration and PNN you get this kind
00:27:15.539 --> 00:27:23.200
of configuration . Now you require to I give
it to the assignment what you have done in
00:27:23.200 --> 00:27:30.570
case of the 3 level 2 level inverter to find
out T a T V dc. I am not deriving here and
00:27:30.570 --> 00:27:37.820
you are expected to derive and the solve it
for T a V T c for the calculations ok. Thank
00:27:37.820 --> 00:27:44.080
you, we shall continue in the next class and
this is our last lectures for the PWM technique,
00:27:44.080 --> 00:27:49.739
for next class onward we shall start with
the actually the facts devices practical fact
00:27:49.739 --> 00:28:15.409
devices and it is control and it is applications.
Thank you .